Welcome to my new blog on AMS SoC Verification

Let's start presenting myself.

I've been working in the semiconductor industry since 1994.
I started as an Applications Engineer at LSI LOGIC.
Then I became a Digital Designer, writing RTL code in VHDL.


In 1998 I joined a small company called CSTI but the company collapsed.
I then joined a Mixed-Signal team at Motorol, which became Freescale.

Since 2003 I started to work full time on the verification of our Mixed-Signal ASICs;
The first SoC's I've been responsible of the verification of were dedicated to Power-Management, User Interface and Audio.

Since 2 years, I've been in charge of the verification of sensor ASICs.

The progresses of the methodology allowed us to go to production with a bunch of first-pass successes.

The methodology I'm using is based on ePlanner to track the coverage progresses and achievements.

The testbench is a mixture of SystemVerilog and Verilog-AMS code.

The SoC itself is simulated at a mixed-level, including transistors and a mix of RTL, wreal and AMS models.