Systemverilog bind is used to instantiate a module into another without having to modify the original code. It is an “out of scope” instanciation. Since this creates a new instance, the bound unit has its own scope, and its internal signal names do not have to match the ones from the target module. The new module communicates with the target through its pins (or with OOMR - Out Of Module Reference).
PSL vunit in opposition, is almost like an `include statement which is added externally to the target module. Similarly the latter does not have to be edited. Like an `include, a vunit does not create its own scope. Hence, the signals inside the vunit have to match the ones of the target module.