Delayed Blocking versus Non-Blocking Assignments

​Hi,

A question that I am often asked is how to write a simple delayed buffer model in verilog, especially when considering its behavior regarding input glitches.

There are several possible coding styles: blocking versus non-block assignments, and delayed evaluation versus delayed assignment.

Here is a little testcase presenting the effect of the 4 possible combinations of code. You will see that the most "natural" behavior is obtained from the third style, using Blocking and delayed assignment.

regards

- Regis

​module tb;

reg in = 1'b0;

initial begin

  #10 in <= 1;

  #10 in <= 0;

  #10 in <= 1;

  #3  in <= 0;

  #3  in <= 1;

  #9  in <= 0;

  #10 $finish;

end

reg o1 = 1'b0;

reg o2 = 1'b0;

reg o3 = 1'b0;

reg o4 = 1'b0;

always @(in) #5 o1  = in; // Blocking,     delayed evaluation (wait 5ns, then evaluate and assign immediately)

always @(in) #5 o2 <= in; // Non-Blocking, delayed evaluation (wait 5ns, then evaluate, then 

always @(in) o3  = #5 in; // Blocking,      delayed assignment

always @(in) o4 <= #5 in; // Non-Blocking,  delayed assignment

//              10   15    20         30  33  36   41   45    50

//              +----------+          +---+   +---------+

// in __________|          |__________|   |___|         |__________

//                   +----------+                   +---------+

// o1 _______________|          |___________________|         |_____

//                   +----------+                   +---------+

// o2 _______________|          |___________________|         |_____

//                                           35

//                   +----------+            +----------------+

// o3 _______________|          |____________|                |_____

//                   +----------+          +---+   +---------+

// o4 _______________|          |__________|   |___|         |__________

endmodule