Systemverilog bind is used to instantiate a module into another without having to modify the original code. It is an “out of scope” instanciation. Since this creates a new instance, the bound unit has its own scope, and its internal signal names do not have to match the ones from the target module. The new module communicates with the target through its pins (or with OOMR - Out Of Module Reference).
PSL vunit in opposition, is almost like an `include statement which is added externally to the target module. Similarly the latter does not have to be edited. Like an `include, a vunit does not create its own scope. Hence, the signals inside the vunit have to match the ones of the target module.
Hi, I need a help in writing assertions of AMS DUT. the signal is declared with wreal datatype. how do i monitor it continuously
RépondreSupprimerHi Paul, If your analog is modeled with wreal, you are in the discrete time domain. You could then use any digital clock. If you plan to swap your wreal model to its actual transistor representation, you could get some hints on my publication here : http://www.cadence.com/cdnlive/library/documents/2013/eu/VER08_Paper_SantojaR_Freescale.pdf. In order for the same assertion code to run flawlessly on both wreal and transistors, I use macros that check the signal's domain before calling either cadence's $cds_get_analog_value (or Synopsys snps_get_volt/$snps_get_port_current) in case continuous, and an easy VPI in case of discrete. For sensitive signals like references, I call these system functions or VPIs based on a clock generated from the analog solver time steps, to ensure I do not miss any analog "hazard". Hope this helps ;-)
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