Using UVM field access policy to manage bit bashing test

Hi,

If you're using UVM Register Layer, you might be interested by the predefined Test Sequences that are provided. I'm going to talk specifically about the uvm_reg_bit_bash_seq sequence. 

It is a bit-bashing test : it sequentially writes "1" dans "0" in each bit of all the registers, checking it is appropriately set or cleared, based on the field access policy.

The UVM 1.1 User Guide explains that the following attributes can be used on a register to skip it from the bit bashing test: NO_REG_BIT_BASH_TEST, NO_REG_TESTS

Unfortunately, these attributes act at register level, and not at field level, which would be useful to exclude individual fields or bits like a soft reset (to prevent the chip shutdown during the test).

Guess what ? In fact you can (exclude inividual fields/bits from the bit bashing). You just have to give your bits/fields the WO (write only) attribute. The test will not attempt to write to it because it has no means to read the written value back (write only means no read).

It is now extremely easy to prevent the soft reset to be triggered by the bit bashing test.

Note: you can also use these other filed attributes: WOC, WOS, WO1.