A few words about assertions, coverpoints and Verification Plan

Hi,

It might not be crystal clear how to use assertions and coverpoints, having in mind that these metrics are meant to be bound to a Verification Plan.​

Let's take an example. We have a 8 bit register in the design (a counter or whatever): 

• We want to make sure each time the register value changes, it is as expected. somehwere in the bench you'd calculate the expected value, and an assertion would make sure expected and actual values always match.
• But how do you know if all possible values of your register were actually verified ?
• Bad idea: create one assertion per possible value. Any non-triggered assertion would tell you what was not covered. But of course 8 bits would need you to create 256 assertions... And what if N is 32 bits or more ???
• Better: create a coverpoint that will give you an exhaustive status of the values that have actually been those of you register. In parallel a single "equation based" assertion would be enough.
• You would then bind both the assertion and the coverpoint to yout vPlan.

Hope this helps,

regards

- regis